Architecture and Implementation of the Load-Reducing DIMM (LRDIMM)

In the past two years, as DDR3 technology was released with high hopes of significant performance boosts over its predecessor, it became apparent that signal integrity of the system buses, especially the system data bus, was now the limiting factor on performance. In existing system platforms, the register on the Registered DIMM (RDIMM) mitigates the significant problem of loading on the system address, control and clock distribution. However, even for DDR3 RDIMM, the multiple data loads per DIMM on the system data bus dictates population rules and operating frequency, resulting in limitations on capacity or bandwidth for the end user.

In this tutorial, we examine the solution that resolves the problem of forcing the end user to chose between capacity and bandwidth. The solution being proposed involves the introduction of a new type of memory module, a Load Reducing DIMM (LRDIMM).  The LRDIMM is designed to be form-factor and infrastructure compatible with RDIMM so that a platform designed to support RDIMM can also support an LRDIMM.  In the place of the register chip on an RDIMM, the LRDIMM uses an Isolation Memory Buffer (iMB) that isolates the electrical loading of the memory devices.  The LRDIMM solves the problem of limitations on operating frequency caused by the presence of multiple data loads per DIMM by presenting a single electrical load on all interfaces where the iMB isolates and normalises the DIMM data bus loads of multiple ranks in addition to the CA/CLK. Extensive analysis of the signal integrity across the complete memory sub-system from  host controller to the DIMMs taking into account all the possible configurations is required in order to optimise the bus topology and termination strategies.

This tutorial will cover the following topics:

Introduction to server memory systems

  • Terminology and JEDEC standardisation
  • Structure of memory systems and DIMMs
  • Ranks, banks, raw cards and risers
  • Configuration rules
  • UDIMM and RDIMM design
  • Specifications and frequencies
  • Performance metrics

Simulation methodology

  • Static timing compared to eye plots
  • Tools and techniques
  • Corners and dimensions
  • Bit error rates and result analysis

LRDIMM advantages

  • Load reduction in isolation
  • Capacity
  • Power
  • System simplification
  • Performance and latency

The anatomy of the iMB at the heart of the DIMM

  • Initialisation
  • Training and leveling
  • CA and clocking
  • MRS cycles
  • Data path and FIFO's
  • Margin testing capabilities
  • HVM test solutions

Conclusion and wrap-up, questions

About the presenter:

Chris Haywood is the Chief Architect at Inphi Corporation and is currently leading the architectural efforts to implement Load-Reducing DIMM for DDR3 memory systems, based on existing DDR3 platforms and infrastructure. At Inphi Corporation, Chris has led numerous other efforts to implement and improve industry standards-based memory systems. Chris's efforts contributed directly to the industry's first DDR3 register in 2006 and first memory buffer (iMB) in 2009.

Prior to joining Inphi Corporation, Chris was the Vice President of Engineering at Internet machines from 2000 to 2004, working on a complete protocol-independent solution for implementing packet processing, traffic management and switching in next generation networking systems. Previously Chris worked at Xylan Corp from 1993 to 2000 and was part of the architecture team that developed the concept of network switching; subsequently becoming hardware engineering design manager. Chris has also held design positions in the US, Ascom Hasler AG, Berne and in the UK.